FIELD OF THE INVENTION
The invention relates to a method for repairing defective memory cells of an integrated semiconductor memory.
The U.S. Pat. No. 5,410,687 describes such a method. Individual memory cells of a memory are tested, wherein the memory cells are situated at crossover points of rows and columns. For each column and each row, the memory has a defect counter in which the defects that are detected for this column or row, respectively, are summed. Once all of the memory cells have been tested, defective memory cells are repaired through the use of redundant column and row lines on the basis of the information items stored in the defect counters. The defect counters required for its implementation require a relatively large amount of space.
The U.S. Pat. No. 5,206,583 describes an integrated circuit which has fuses for a permanent programming of redundant elements. The integrated circuit furthermore has reversibly programmable elements in the form of latches, which are connected in parallel with the fuses and serve, for test purposes, for reversibly programming the redundant elements.